MediaTek USA Inc. | United States
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🔬📡 JEN-CHIEH (JACK) HSUEH: PIONEERING ANALOG/RF INNOVATION IN THE NANO ERA
🎓 EARLY ACADEMIC PURSUITS
Jen-Chieh (Jack) Hsueh began his academic journey in Taiwan, earning his Master of Science in Electrical Engineering from the Graduate Institute of Electronics Engineering (GIEE) at National Taiwan University in 2014. Under the mentorship of Prof. Liang-Hung Lu, his master's thesis, "A Three-Channel True-Time Delay Beamforming Analog Front-End", laid the foundation for his deep dive into high-frequency circuit design and advanced analog front-end systems.
Driven by curiosity and academic rigor, he advanced to The Ohio State University, USA, where he pursued a Ph.D. in Electrical Engineering (2017–2023). Guided by Prof. Waleed Khalil, his doctoral research explored time-based sensor architectures for process attestation and device fingerprinting, focusing on back-end-of-line (BEOL) resistance and capacitance — an emerging field with implications for chip security and authenticity.
💼 PROFESSIONAL ENDEAVORS
Currently a Staff Engineer at MediaTek (since January 2023), Jack contributes his expertise in WIFI G-band PAD design using 6nm process technology. His work involves the full analog IC design flow, addressing process constraints and optimizing trade-offs to ensure reliability, manufacturability, and performance.
With hands-on experience in both legacy and cutting-edge technology nodes (22FDX to 6nm), Jack excels in tools like Cadence Spectre-RF, EMX, Virtuoso Layout Editor, and system design environments like MATLAB and ADS. His seamless transition from academia to industry reflects his applied skillset and future-forward mindset.
🧠 CONTRIBUTIONS AND RESEARCH FOCUS ON NETWORK SECURITY
Jack’s research stands at the confluence of analog/RF circuit design and IC security. His Ph.D. work delivered a highly digital, low-overhead, time-based sensor that identifies chips using their unique physical characteristics — a notable innovation for hardware-level security.
In addition, he has designed high-performance analog/RF systems through various course projects and tape-outs in state-of-the-art processes. Highlights include:
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Ultra-Low Phase Noise VCO in 22nm FDSOI with outstanding performance
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High IIP2 Mixer for direct conversion receiver design with exceptional linearity
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Ultra-Wideband LNA covering 3–10 GHz with optimized noise figure and gain
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28Gb/s High-Speed I/O Interface with feed-forward and decision feedback equalization
Each project demonstrates his mastery in integrating theory with practical, manufacturable circuit solutions.
🌍 IMPACT AND INFLUENCE
Jack’s work significantly contributes to the evolution of chip-level authentication, low-power analog front-end design, and next-generation wireless communication systems. His ability to design circuits with minimal power overhead while preserving signal fidelity and robustness marks him as an innovator in secure and scalable microelectronics.
His designs push the boundaries of signal processing, analog layout, and system integration, especially in a world increasingly dependent on miniaturized, efficient, and secure hardware.
📚 ACADEMIC CITES AND PUBLIC RECOGNITION
While Jack is early in his post-Ph.D. phase, his research on device fingerprinting using BEOL components holds potential for significant citations in chip security, analog IC design, and sensor research domains. As he begins publishing and contributing more broadly, his name is expected to rise among RFIC and VLSI researchers.
His association with reputed institutions — National Taiwan University, The Ohio State University, and MediaTek — adds weight to his work’s credibility and future reach.
🏅 LEGACY AND FUTURE CONTRIBUTIONS
Jack’s evolving career showcases a balanced blend of theoretical depth and industry-ready skills. His legacy will likely be shaped by:
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Securing IC designs against counterfeiting through process-aware fingerprinting
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Pioneering low-power, high-performance RF systems in modern nodes
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Mentoring emerging circuit designers, sharing his journey from academic labs to global semiconductor firms
With his openness to relocation and global outlook, Jack is poised to make cross-border contributions in research, product development, and academic collaboration.
🔧 TOOLS AND TECHNOLOGY PROFICIENCY
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Analog Design Tools: Cadence Spectre/Spectre-RF, EMX, Virtuoso Layout Editor
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System Simulation: MATLAB, ADS, Simulink
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Process Expertise: 22FDX, 22nm FDSOI, 6nm nodes
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Design Flow: DRC, LVS, PEX, IC Layout and Simulation
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Applications: VCOs, Mixers, LNAs, High-Speed Transceivers
🚀 SUMMARY
Jen-Chieh (Jack) Hsueh stands as a promising leader in analog/RF circuit design, blending his deep academic foundation, cutting-edge R&D experience, and practical industry exposure. His future contributions are likely to shape how chips communicate, secure themselves, and operate efficiently in increasingly complex environments.
📑NOTABLE PUBLICATIONS
"In Situ Time-Based Sensor for Process Identification Using Amplified Back-End-of-Line Resistance and Capacitance"
- Authors: Jen-Chieh Hsueh, Mike Kines, Yousri Ahmed Tantawy, Dale Shane Smith, Jamin McCue, Brian Dupaix, Vipul J Patel, Waleed Khalil
- Journal: Sensors
- Year: 2025
"Novel Device Fingerprinting Sensor Leveraging Back-End-of-Line Resistance and Capacitance"
- Authors: Jen-Chieh Hsueh, Michael Kines, Sam Ellicott, Shane Smith, Waleed Khalil
- Journal: IEEE
- Year: 2024
"A Process Attestation and Device Fingerprinting Time-Based Sensor Leveraging Back-End-of-Line Resistance and Capacitance"
- Authors: Jen-Chieh Hsueh
- Journal: Electronics
- Year: 2023
"An ultra-low voltage chaos-based true random number generator for IoT applications"
- Authors: Jen-Chieh Hsueh, Vanessa H-C Chen
- Journal: Microelectronics journal
- Year: 2019
"Instantaneous in‐band radio frequency interference suppression using non‐linear folders"
- Authors: E Chen, J‐C Hsueh, V Chen
- Journal: Electronics Letters
- Year: 2019